The present invention relates generally to semiconductor devices, and more particularly to a double-diffused MOS (DMOS) power transistor.
In a conventional DMOS power transistor 10 formed with a single p-body implant 12, as shown in FIG. 1, a trade-off exists between the threshold voltage (VT) and the pinched-body sheet resistance. A low threshold voltage is attractive for ease of gate drive and low source-to-drain on-state resistance, necessitating a body region 14 with a low surface concentration and/or short channel. These attributes imply high body sheet resistance which makes the parasitic NPN bipolar transistor, shown at 16 with the p-body 12 as base, susceptible to easy turn-on. Activation of the parasitic bipolar transistor results in restricting the transistor safe operating area (SOA) of the power transistor 10, and renders the power transistor unusable for simultaneous high current/high voltage application, when, for example, switching off an inductive load.
Other known ways of dealing with this trade-off are to use of a very deep p-type diffusion in addition to the p-body diffusion, and to use high energy MeV ion implantation to form a retrograde body.
The present invention achieves technical advantages as a double-diffused MOS (DMOS) power transistor having a channel compensating implant. A shallow n-type channel compensating implant (NCCI) is employed to decouple the p-body surface concentration and pinched body sheet resistance. The doping of the NCCI overcompensates the lighter doped portion of the graded p-body, making it n-type. This results in partial compensation of the heavy doped p-body near the transistor n+source, achieving a shorter, more lightly doped channel with the same heavy doped p-body beneath the n+transistor source. The power transistor of the present invention gives a more favorable trade-off between threshold voltage/on-state resistance and safe operating area. The NCCI allows a larger fraction of the transistor bias voltage to be supported on the thin gate oxide proximate the transistor gate. The present invention achieves further technical advantages as it can be fabricated using a self-aligned technique with a channel length that is insensitive to lithography techniques.